1. Field of Invention
Apparatuses and methods consistent with the present invention relate to a semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.
2. Description of the Related Art
Conventional methods of forming a semiconductor package comprising a flip chip and a substrate involves mounting a chip 10 with solder bumps 12 onto a top surface of the substrate 14. When mounted, the solder bumps 12 of the chip 10 are in contact with the substrate 14 and gaps are formed between the chip 10 and the substrate 14 due to the solder bumps 12 present therebetween. The gaps between the chip 10 and the substrate 14 would typically be underfilled with an underfill resin 16 to encapsulate and to protect the solder bumps 12. The chip 10 and top surface of the substrate 14 are then encapsulated with a mold resin 18 to protect the chip 10. External package connections in the form of solder balls 20 are subsequently formed on a bottom surface of the substrate 14. An exemplary flip chip package is shown in FIG. 8 of the drawings. In the conventional package, the solder bumps 12 and solder balls 20 may be subjected to mechanical stress resulting from differential thermal expansions of the various components of the package under application of heat during thermal cycling or when the chip is in operation.
In U.S. Pat. No. 7,271,491, a carrier substrate with apertures is provided on a semiconductor device such that bond pads are aligned with apertures. Semiconductor device is a flip-chip device that has bond pads disposed over active surface. Walls of the apertures and the bond pads are coated with a conductive material. Solder material is provided at the opening of the apertures to result in the solder material filling the coated apertures by capillary action and forming solder bumps. However, in this method, there may be reliability issues resulting from inadequate contact between bond pad, the conductive coating and the solder material within the apertures.
In U.S. Pat. No. 6,022,761, a substrate is provided with apertures in which the openings on underside covered with conductive metal pads. An interposer with an array of conductive bumps is mounted onto the substrate such that the adhesive bumps resides in the apertures. A semiconductor device with an array of conductive bumps is pressed into contact with the interposer such that the conductive bumps are coupled to the conductive adhesive bumps to form the package as shown below. However, in this method, the conductive bumps and active circuitry of the semiconductor device while being pressed into contact with the interposer. Also, there may be reliability issues resulting from voids formed within the apertures should the adhesive bumps not fill the apertures adequately. Another problem may also be that the adhesive bumps may not adequately contact the metal pads to form a reliable electrical connection.
In U.S. Patent Application No. 2006/0057833, a substrate is provided with screen mask such that the wire ball bumps on the substrate fits into the apertures of the screen mask. Solder paste is spread over the mask to embed the wire ball bumps. The screen mask is then removed and the solder paste reflowed to form solder ball connections. However, this method is focused on forming external package connections in the form of solder balls rather than forming an improved electrical interconnect between the flip chip and the external package connections.
There is therefore a need to provide apparatuses and methods that can prevent or at least ameliorate one or more of the disadvantages of the prior art. One objective of the present invention is to reduce the stress on the bumps of flip chip. Another objective is to eliminate underfilling, which results in a saving of material costs.